1. Field of the Invention
The invention relates to a clock distribution system, and in particular to a phase-locked loop in the clock distribution system and a method thereof.
2. Description of the Related Art
A phase-locked loop (PLL) is a closed loop control system maintaining a fixed phase relationship between a generated signal and a reference signal. In high speed applications, a high-speed and low-noise PLL is required in a clock distribution system to meet clock speed requirements. For example, in a multilane system, a global clock multiplier unit (CMU) produces a transmitter clock shared by multiple lanes, and is realized by a high-speed and low-noise PLL.
FIG. 1 is a block diagram of a conventional PLL with noise sources, comprising Phase Frequency Detector/Charge Pump (PFD/CP) 10, filter 12, and Voltage Controlled Oscillator (VCO) 14. PFD/CP 10 is coupled to filter 12, and in turn coupled to VCO 14.
VCO 14 varies output frequency fout1 in response to control voltage Vc1 and generates periodic output. If output frequency fout1 falls behind that of the reference, PFD/CP 10 detects frequency difference therebetween, and changes control voltage Vc1 to speed output frequency fout1 from VCO 14. Likewise, if output frequency fout1 leads the reference, PFD/CP 10 changes control voltage Vc1 to slow down output frequency fout1 from VCO 14. Filter 12 smoothes any abrupt change in control voltage Vc1, so that PLL system 1 tends towards a state where PFD/CP 10 makes few corrections.
As device sizes of integrated circuits are reduced, operating voltage ranges thereof decrease accordingly, yet the required frequency ranges increase. Therefore VCO gain KVCO of the VCO 14 is increased to cover the required frequency range in the limited voltage range. The process, voltage, and temperature (PVT) variation in integrated circuits further introduces a need for higher VCO gain KVCO. FIG. 2 shows a control voltage Vc1 and output frequency fout1 (V-f) curve of the VCO in FIG. 1, comprising curves ss, tt, and ff for three process corners. High gain KVCO is deployed so that the required frequency range from f1 to f2 can be covered for all process variation in FIG. 2. Unfortunately the high VCO gain KVCO also amplifies control voltage noise nc, resulting in severer phase noise or jitter in output frequency fout1.
Referring now to FIG. 1, the phase noise in output frequency fout1 comprises control voltage noise nc at node n10 and local VCO noise nl at node n12. Control voltage noise nc includes charge pump noise nCP and power-ground noise nPG, and is amplified by VCO gain KVCO, contributing to the phase noise of output frequency fout1. Local VCO noise nl includes VCO noise nVCO and power-ground noise nPG, and is not amplified by VCO gain KVCO. Control voltage noise nc contributes a major part in the phase noise of output frequency fout1 due to the high VCO gain KVCO, therefore reduction in control voltage noise nc improves the phase noise significantly. Power-ground noise nPG may be reduced through decoupling capacitors or shielding, leaving charge pump noise nCP as the dominant part in control voltage noise nc. Charge pump noise nCP results from accumulative noise of circuit deficiency before node n10, including charge sharing, current mismatch, clock feedthrough, charge injection, reference signal spur, and current switching noise.
FIG. 3 shows control voltage Vc1 and output frequency fout1 (V-f) curves of the VCO in FIG. 1 to reduce the phase noise, deploying low VCO gain KVCO and multiple V-f curves covering the frequency range from frequency f1 to frequency f2, as disclosed in “A CMOS self-Calibrating Frequency Synthesizer”, IEEE journal of Solid State Circuits, Vol. 35, No. 10, October 2000, and “A 900-MHz 2.5-mA CMOS Frequency Synthesizer with an Automatic SC Tuning Loop”, IEEE journal of Solid State Circuits, Vol. 36, No. 3, March 2001. VCO employing the approach in FIG. 3 determines a voltage range of control voltage Vc, and selects a corresponding V-f curve to produce corresponding output frequency fout1. The phase noise of output frequency fout1 is reduced by the low VCO gain KVCO, at the expense of circuit complexity and manufacturing cost. Furthermore, the additional circuit complexity of VCO may contribute to higher VCO noise, directly associated with the phase noise of output frequency fout1. Consequently the phase noise reduction in FIG. 3 is limited.
Thus a PLL in a clock distribution system that generates high-speed and low-noise clock is called for.